Counters

Chain some flip-flops together and their outputs, read as a binary number, go up by one every clock edge. That is the entire idea, and everything else on this page is a variation on it.

The rule that makes it count

A counter has one flip-flop per bit, and each one toggles when every bit below it is high. That single rule is binary counting: the ones column flips every time, the twos column flips every second time, the fours column every fourth time. Nothing keeps a running total anywhere.

Every state of a 3 bit counter, and which bits toggle on the next edge
Count	Q2	Q1	Q0	Toggles next
0	0	0	0	Q0
1	0	0	1	Q1, Q0
2	0	1	0	Q0
3	0	1	1	Q2, Q1, Q0
4	1	0	0	Q0
5	1	0	1	Q1, Q0
6	1	1	0	Q0
7	1	1	1	Q2, Q1, Q0

A counter wrapping back to zero is just fixed-width binary running out of room, which the binary converter shows directly. Read the last column down and you have the wiring: Q0 always toggles, so its T input is tied high. Q1 toggles when Q0 is high, so its T input is Q0. Q2 toggles when Q0 and Q1 are both high, so its T input is one AND gate. That pattern continues for as many bits as you want.

What it looks like in time

Each bit runs at half the rate of the one below it. That halving is why a counter is also a frequency divider, and it is how a 32768 Hz crystal becomes a one second tick in a watch: fifteen stages of division.

Q0 toggles every cycle, Q1 every second cycle, Q2 every fourth. The counter wraps back to 0 after 7.

The four you will meet

Ripple (asynchronous)

Each flip-flop clocks the next one.

The simplest to wire and the cheapest in gates, but each stage waits for the one before it, so the delays add up and the outputs pass through wrong intermediate values whenever a carry ripples — worst at the wrap from all ones back to zero, where every stage changes in turn. Fine for driving a display, not for feeding other logic.

Synchronous

Every flip-flop shares one clock.

All the stages change together, so the count is valid one propagation delay after the edge no matter how wide the counter is. It costs extra AND gates to work out which stages should toggle, which is the usual trade.

Decade (mod 10)

Counts 0 to 9, then clears.

A four bit counter with a detector on the state after the last one you want, wired to the clear input. The same trick gives any modulus, which is how a clock divides seconds into minutes.

Up/down

One control line picks the direction.

Counting down is counting up with every bit inverted on the way into the toggle logic, so the same circuit does both with a multiplexer choosing between Q and its complement.

Counting to something that is not a power of two

A chain of n flip-flops naturally runs through all 2ⁿ of its states, counting 0 to 2ⁿ − 1. To stop anywhere else you watch for the state just past the last one you want and use it to clear the counter. A decade counter is four bits with a detector on 10, so the sequence runs 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and then starts again.

The same shape as a four bit counter until 9, where the clear cuts the sequence short and the count restarts.

The detector is a single AND gate on the bits that are high in the state you are catching. That state exists for a moment before the clear takes effect, which is a real glitch on the outputs and the reason a synchronous clear is preferred where anything downstream is watching. Where those glitches matter more than the count being readable, a Gray code counter changes only one bit per step and so has none.

Designing one that counts in your own order

A counter does not have to count in binary. Write down the sequence of states you want, look up each transition in the excitation table of whichever flip-flop you are using, and you have a truth table for each input: what to put on it, given the present state. Minimise those tables and the gates fall out.

List the states in the order you want them, and the state each one goes to.
Look up the inputs for each transition. For a T flip-flop that is just "did this bit change", which is why T is the easy choice for counters.
Minimise each input's table with a Karnaugh map or the algebra calculator.
Build it and check it goes round: the simulator has a counter node, and flip-flops you can wire from gates. The common circuits reference has the decoders and comparators you will want around it.

Build a counter in the simulator

Reference cards

Both waveforms as images, black on white, for notes or a slide.

Timing diagram of a 3 bit binary counter, showing Q0 toggling every cycle, Q1 every second cycle and Q2 every fourth

Click to download: 3 bit binary counter timing diagram

Timing diagram of a decade counter counting 0 to 9 and clearing back to 0

Click to download: Decade counter timing diagram

Questions about counters

What is a counter in digital logic?

A chain of flip-flops whose outputs, read as a binary number, go up by one on every clock edge. Nothing counts the pulses in any deeper sense: each stage simply toggles when all the stages below it are high, and that rule is exactly what binary counting is.

What is the difference between a ripple counter and a synchronous counter?

In a ripple counter each flip-flop is clocked by the one before it, so the change ripples along the chain and the outputs pass through wrong intermediate values whenever a carry ripples, worst of all at the wrap back to zero. In a synchronous counter every flip-flop shares the clock and extra AND gates decide which ones toggle, so all the bits change together. Ripple is cheaper; synchronous is correct at speed.

How do I build a counter that stops at a number that is not a power of two?

Detect the state just past the last one you want and use it to clear the counter. A decade counter is a four bit counter with an AND gate watching for 10 and wired to the clear input, so the count runs 0 to 9 and starts again. The same trick gives any modulus.

How many flip-flops does an n bit counter need?

One per bit, so n flip-flops give 2^n states, counting 0 to 2^n - 1: three flip-flops count 0 to 7, four count 0 to 15, eight count 0 to 255. To count up to a number m that is not a power of two you need enough bits to hold m, so ceil(log2(m)) flip-flops plus the gate that clears it.

Why does the top bit of a counter run at half the speed of the one below it?

Because each bit toggles once for every two toggles of the bit below. That halving is why a counter is also a frequency divider: the most significant bit of an n bit counter is the clock divided by 2^n, which is how a 32768 Hz crystal becomes a one second tick in a watch.