The SR latch
Two gates, each feeding the other, and suddenly a circuit can remember. The SR latch is the smallest piece of memory in digital logic and the idea inside every flip-flop, register and static RAM cell.
What a latch is
A latch is a circuit with two stable states that stays in whichever one it was last pushed into. That is all memory means at the level of gates: a value that persists after the input that caused it has gone away. Every gate on the gates page is combinational, its output fixed by its inputs right now. A latch escapes that by feedback. Route a gate's output back round to an input and the circuit's present output becomes one of the things that decides its next output, so it has a past.
The SR latch has two inputs, set and reset, and an output Q. Pulse set and Q becomes 1 and stays 1. Pulse reset and Q becomes 0 and stays 0. Leave both inputs alone and Q holds. Its complement Q̄ is available on the other gate for free.
The NOR SR latch
Two cross-coupled NOR gates. Active-high set and reset.
Take two NOR gates. The output of each goes into one input of the other, and the two inputs left over are S and R. Call the gate that takes R the Q gate, and the gate that takes S the Q̄ gate. A NOR outputs 1 only when both of its inputs are 0, so with S and R both low each gate is held by the other: if Q is 1, the Q̄ gate sees that 1 and outputs 0, and the Q gate sees R = 0 and Q̄ = 0 and keeps Q at 1. Raise S and the Q̄ gate is forced to 0, so the Q gate now sees two 0s and goes to 1: the pair has flipped, and dropping S again leaves it there. Raising R forces the Q gate to 0 in the same way.
| S | R | Q | Q⁺ | Effect |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | hold |
| 0 | 0 | 1 | 1 | hold |
| 0 | 1 | 0 | 0 | reset |
| 0 | 1 | 1 | 0 | reset |
| 1 | 0 | 0 | 1 | set |
| 1 | 0 | 1 | 1 | set |
| 1 | 1 | 0 | — | not allowed |
| 1 | 1 | 1 | — | not allowed |
Q⁺ = S ∨ (¬R ∧ Q)
Q⁺ is the state the latch settles into; X means the input does not matter. The equation is the table written as algebra, and the diagram below is simulated from it.
The NAND SR latch
Two cross-coupled NAND gates. Set and reset are active-low: a 0 does the work.
The same wiring with NAND gates gives a latch that is set and reset by a 0 rather than a 1, because a NAND output is forced, to 1, only when an input goes low. Its inputs are therefore written S̄ and R̄, both sit at 1 when idle, and a 0 on S̄ sets while a 0 on R̄ resets. It is the same machine with the polarity flipped, and the more common of the two inside real chips, since NAND is the smaller and faster gate in CMOS.
| S̄ | R̄ | Q | Q⁺ | Effect |
|---|---|---|---|---|
| 1 | 1 | 0 | 0 | hold |
| 1 | 1 | 1 | 1 | hold |
| 1 | 0 | 0 | 0 | reset |
| 1 | 0 | 1 | 0 | reset |
| 0 | 1 | 0 | 1 | set |
| 0 | 1 | 1 | 1 | set |
| 0 | 0 | 0 | — | not allowed |
| 0 | 0 | 1 | — | not allowed |
Q⁺ = ¬S̄ ∨ (R̄ ∧ Q)
Q⁺ is the state the latch settles into; X means the input does not matter. The equation is the table written as algebra, and the diagram below is simulated from it.
The gated SR latch
An SR latch behind an enable. While E is low, S and R are ignored.
Put an AND gate in front of each input and feed an enable line E into both, and the latch only listens while E is high. While E is low, S and R can do what they like and Q holds. This is the step towards a flip-flop: instead of responding at any moment, the latch responds only during a window that something else controls.
| E | S | R | Q | Q⁺ | Effect |
|---|---|---|---|---|---|
| 0 | X | X | 0 | 0 | hold: disabled |
| 0 | X | X | 1 | 1 | hold: disabled |
| 1 | 0 | 0 | 0 | 0 | hold |
| 1 | 0 | 0 | 1 | 1 | hold |
| 1 | 0 | 1 | 0 | 0 | reset |
| 1 | 0 | 1 | 1 | 0 | reset |
| 1 | 1 | 0 | 0 | 1 | set |
| 1 | 1 | 0 | 1 | 1 | set |
| 1 | 1 | 1 | 0 | — | not allowed |
| 1 | 1 | 1 | 1 | — | not allowed |
Q⁺ = (E ∧ S) ∨ (¬(E ∧ R) ∧ Q)
Q⁺ is the state the latch settles into; X means the input does not matter. The equation is the table written as algebra, and the diagram below is simulated from it.
The D latch
A gated SR latch with R tied to ¬S. Transparent while E is high, frozen while it is low.
Tie the reset of a gated SR latch to the inverse of its set, so that a single data line D drives both, and the forbidden combination can no longer happen. While E is high, Q simply copies D, which is why this is also called a transparent latch. When E drops, Q freezes at whatever D was last. Two of these back to back, enabled on opposite halves of a clock, make an edge-triggered D flip-flop.
| E | D | Q | Q⁺ | Effect |
|---|---|---|---|---|
| 0 | X | 0 | 0 | hold: frozen |
| 0 | X | 1 | 1 | hold: frozen |
| 1 | 0 | 0 | 0 | follows D |
| 1 | 0 | 1 | 0 | follows D |
| 1 | 1 | 0 | 1 | follows D |
| 1 | 1 | 1 | 1 | follows D |
Q⁺ = (E ∧ D) ∨ (¬E ∧ Q)
Q⁺ is the state the latch settles into; X means the input does not matter. The equation is the table written as algebra, and the diagram below is simulated from it.
The forbidden input
Raise S and R together on a NOR latch and both gates are forced to 0, so Q and Q̄ are both 0 and no longer opposites. That alone breaks anything downstream that relied on one being the inverse of the other. The real trouble comes when the two inputs then fall at the same moment: each gate wants to go high if the other stays low, and which one wins depends on which is a fraction of a nanosecond faster. The latch may settle either way, or even oscillate briefly. The state after that is not predictable, which is why the row is marked as not allowed rather than filled in. The JK flip-flop exists largely to give that input combination a meaning: toggle.
Latch or flip-flop?
A latch is level sensitive. It responds to its inputs whenever they change, for as long as they stay changed, and in the gated versions whenever the enable is high. A flip-flop is edge triggered: it samples its inputs at the instant of a clock edge and ignores them at every other moment. That difference is the whole reason clocks exist. With a latch, a signal that changes twice while the enable is high gets through twice; with a flip-flop it is seen exactly once per cycle, at a predictable instant, and everything downstream can be designed around that instant. The combinational vs sequential page has the longer version.
Where it is used
- Switch debouncing. A mechanical switch bounces for milliseconds. Wire the two contacts of a changeover switch to set and reset and the latch flips on the first touch and ignores every bounce after it.
- Fault and alarm flags. A condition that lasted a microsecond sets the latch, and the flag stays up until something explicitly resets it.
- Arbitration. Two requests race for a resource; whichever sets the latch first wins and holds it.
- Inside every flip-flop. D, JK and T flip-flops are classically an SR latch with logic in front of it, and a static RAM cell is the same feedback loop, two cross-coupled inverters, behind two access transistors.
Build one
Two NOR gates, two toggles and two displays, with each gate's output wired back into the other's input. Set and reset it, then try both inputs high and watch what happens when you release them. Seeing the feedback path settle is worth more than reading about it.
It is step 5 of the learning path. The clocked version, with its characteristic and excitation tables and a demo you can clock, is on the SR flip-flop page.
Questions about the SR latch
What is an SR latch?
The simplest circuit that remembers one bit. Two cross-coupled gates, each feeding an input of the other, give it two stable states. A pulse on the set input drives the output to 1 and it stays there; a pulse on reset drives it to 0 and it stays there. With neither input active the latch holds its last value, which is what makes it memory.
How do you build an SR latch from NOR gates?
Take two NOR gates. Connect the output of the first to one input of the second, and the output of the second to one input of the first. The two free inputs are S and R, and the two outputs are Q and its complement. Raising S makes Q go high; raising R makes it go low; both low holds. Both high at once is the one input you must not give it.
How do you build an SR latch from NAND gates?
Exactly the same wiring with NAND gates instead. The difference is polarity: a NAND latch is set and reset by a 0 rather than a 1, so its inputs are written S̄ and R̄, the resting state is both inputs high, and both low is the forbidden case. It is the version most textbooks draw and the one on classic parts such as the 74279 quad latch, since NAND is the cheaper gate in CMOS.
Why is S = R = 1 forbidden on an SR latch?
With both inputs of a NOR latch high, both NOR gates output 0, so Q and Q̄ are both 0 and no longer opposites. Worse, if the two inputs then drop at the same moment, which state the latch settles into depends on which gate happens to be a fraction faster, so the result is unpredictable. Designs either guarantee the combination never happens, or use a JK flip-flop, which turns that case into a toggle.
What is the difference between an SR latch and an SR flip-flop?
A latch is level sensitive: it responds the moment its inputs change, for as long as they stay changed. A flip-flop is edge triggered: it looks at its inputs only at the instant of a clock edge and ignores them the rest of the time. A gated latch is halfway between the two, responding only while an enable line is high. An edge-triggered SR flip-flop is two gated latches in a master-slave pair, driven by opposite phases of the clock, so the output can only move at the edge between them.
What is a D latch?
A gated SR latch with R wired to the inverse of S, so the forbidden input can never happen. The single data input D is copied to Q while the enable is high, which is why it is also called a transparent latch, and Q freezes at its last value when the enable drops. Two D latches back to back, enabled on opposite phases, make an edge-triggered D flip-flop.
What is an SR latch used for?
Debouncing a mechanical switch, holding a fault or alarm flag until it is explicitly cleared, arbitrating between two requests so that whichever arrives first wins, and as the storage element inside flip-flops and registers. Anything that needs to remember a single bit without a clock is a latch of this kind, or something built on the same feedback loop.